Typically, architectures for packet routing devices include pipelined modules or functional unit blocks that each perform operations on the received packets of data. However, such a hardware model is at odds with a processing architecture that is more closely aligned with idealized conceptual models of packet header structures and network operations.
One clear example of such a hardware-centric emphasis on processing architectures is the linear processing pipeline. Often the motivation to adopt a pipeline-like structure is clear. Generally a pipeline, like a factory's assembly line, has multiple packets in process simultaneously; with the packets moving from one specialized processing stage to the next in a rigidly timed lock-step fashion. Unfortunately, the desired packet processing behavior doesn't map neatly to a pipeline owing to the wide variety of possible header configurations.
Pipelines are also typically unable to vary their per-packet processing time. While this usually affords the benefit of easily guaranteeing line-rate performance under all circumstances, this is not necessarily ideal.